?2014. renesas electronics cor poration, all rights reserved. page 1 of 4 renesas technical update 1753, shimonumabe, nakahara-ku, kawa saki-shi, kanagawa 211-8668 japan renesas electronics corporation renesas technical up date tn-rx*-a000a/e date: ) h e . , 2014 this document describes corrections and additions to descri ptions for i/o ports in rx111 group user's manual: hardware. 1. corrections ? page 332 of 1209 descriptions for the port direction register (pdr) in 18.3.1 are corrected as follows: before correction pdr is used to select the input or output direction for individual pins of the corresponding port m when the pins are configured as the general i/o pins. each bit of portm.pdr corresponds to each pin of port m; i/ o direction can be specified in 1-bit units. for software compatibility, 1 (output) can be written to the bits corresponding to port m on the 64-pin product but which do not exist on a product with fewer than 64 pins are reserved. the port3.pdr.b5 bit is reserved, because the p35 pin is input only. the bit corres ponding to a pin that does not exist is also reserved. a reserved bit is read as 0. the write value should be 0. after correction pdr is used to select the input or output direction for individual pins of the corresponding port m when the pins are configured as the general i/o pins. portm.pdr is a direction register of port m. each bit in th is register corresponds to each pin of port m and i/o direction can be specified in 1-bit units. the bits corresponding to pi ns that are not listed in table 18.1 and the port3.pdr.b5 bit of the input-only p35 pin are reserved. a reserved bit should be set to 0 or 1 according to table 18.3. when setting a value to a reserved bit, access in byte units. ? page 333 of 1209 descriptions for the port output data register (podr) in 18.3.2 are corrected as follows: before correction podr holds the data to be output from the pins used for general output ports. bits corresponding to port m on the 64 pin-product but whic h do not exist on a product with fewer than 64 pins are reserved. write 0 to these bits. the port3.podr.b5 bit is reserved, because the p35 pin is input only. the bit corresponding to a pin that does not exist is reserved. a reserved bit is read as 0. the write value should be 0. after correction podr holds the data to be output from the pins used for general output ports. the bits corresponding to pins that are not listed in tabl e 18.1 and the port3.podr.b5 bit of the input-only p35 pin are reserved. a reserved bit is read as 0. the write value should be 0. when setting a value to a reserved bit, access in byte units. product category mpu & mcu document no. tn-rx*-a0 a/e 5 ev. .00 title corrections and additions to the rx111 group user?s manual: hardware regarding i/o ports information category technical notification applicable product rx111 group lot no. reference document rx111 group user's manual: hardware rev.1.00 (r01uh0365ej0100) all
page 2 of 4 renesas technical update tn-rx*-a0 a/e date: feb. 25, 2014 ? page 334 of 1209 ?r/w? in the r/w column of b0 to b7 in the table for the port input data regi ster (pidr) in 18.3.3 is corrected to ?r?. ? page 334 of 1209 descriptions for the port input data register (pidr) in 18.3.3 are corrected as follows: before correction pidr indicates individual pin states of port m. the pin states of port m can be read with the portm.pidr, regardless of the values of portm.pdr and portm.pmr. the nmi pin state is reflected in the p35 bit. the bit corresponding to a pin that does not exist is reserved. a reserved bit is read as undefined and cannot be modified. after correction pidr indicates individual pin states of port m. the pin states of port m can be read with the portm.pidr, regardless of the values of portm.pdr and portm.pmr. the nmi pin state is reflected in the p35 bit. the bits corresponding to pins that are not listed in table 18. 1 are reserved. the read value of a reserved bit is undefined. writing has no effect. ? page 335 of 1209 descriptions for the port mode register (p mr) in 18.3.4 are co rrected as follows: before correction each bit of portm.pmr corresponds to each pin of po rt m; pin function can be specified in 1-bit units. bits corresponding to port m on the 64 pin-product but which do not exist on a product with fewer than 64 pins are reserved. write 0 to these bits. the bit corresponding to a pin that does not exist is reserved. a reserved bit is read as 0. the write value should be 0. after correction each bit of portm.pmr corresponds to each pin of po rt m; pin function can be specified in 1-bit units. the bits corresponding to pins that are not listed in table 18.1 and the port3.pmr.b5 bit of the input-only p35 pin are reserved. a reserved bit is read as 0. the write value should be 0. when setting a value to a reserved bit, access in byte units. ? page 336 of 1209 descriptions for the open drain control register 0 (odr0) in 18.3.5 are corrected as follows: before correction bits corresponding to port m on the 64 pin-product but whic h do not exist on a product with fewer than 64 pins are reserved. write 0 to these bits. the bit corresponding to a pin that does not exist is reserved. a reserved bit is read as 0. the write value should be 0. after correction the bits corresponding to pins that are not listed in table 18.1 are reserved. a reserved bit is read as 0. the write value should be 0. when setting a value to a reserved bit, access in byte units. ? page 337 of 1209 descriptions for the open drain control register 1 (odr1) in 18.3.6 are corrected as follows: before correction bits corresponding to port m on the 64 pin-product but whic h do not exist on a product with fewer than 64 pins are reserved. write 0 to these bits. the port3.odr1.b2 bit is reserved, because the p35 pin is in put only. the bit corr esponding to a pin that does not exist is reserved. a reserved bit is read as 0. the write value should be 0. after correction the bits corresponding to pins that are not listed in table 18.1 and the port3.odr1.b2 bit of the input-only p35 pin are reserved. a reserved bit is read as 0. the write value should be 0. when setting a value to a reserved bit, access in byte units.
page 3 of 4 renesas technical update tn-rx*-a0 a/e date: feb. 25, 2014 ? page 338 of 1209 descriptions for the pull-up control register (pcr) in 18.3.7 are corrected as follows: before correction while a pin is in the input state with th e corresponding bit in portm.pcr set to 1, the pull-up resistor connected to the pin is enabled. when a pin is set as a general port output pin, or a peripheral function output pin, the pull-up resistor for the pin is disabled regardless of the settings of pcr. the pull-up resistor is also disabled in the reset state. the port3.pcr.b5 bit is reserved. the bit corresponding to a pin that does not exist is reserved. a reserved bit is read as 0. the write value should be 0. after correction while a pin is in the input state with th e corresponding bit in portm.pcr set to 1, the pull-up resistor connected to the pin is enabled. when a pin is set as a general port output pin, or a peripheral function output pin, the pull-up resistor for the pin is disabled regardless of the settings of pcr. the pull-up resistor is also disabled in the reset state. the bits corresponding to pins that are not listed in table 18.1 and the port3.pcr.b5 bit are reserved. a reserved bit is read as 0. the write value should be 0. when setting a value to a reserv ed bit, access in byte units. 2. additions 18.4 is added as follows: 18.4 initialization of the port direction register (pdr) initialize reserved bits in the pdr register according to table 18.3 to table 18.6. ? the blank columns in table 18.3 to ta ble 18.6 indicate th e bits corresponding to the pins listed in table 18.1, i/o port specifications. the corresponding bits should be set to 1 (output) or 0 (input) depending on the user system. however, the port3.pdr.b5 bit of the input-only p35 pin is reserved. this bit should be set to 0 (input). ? the columns other than the blank columns in table 18.3 to table 18.6 indicate reserved bits. a reserved bit should be set to 0 (input) or 1 (output) according to ta ble 18.3 to table 18.6. when setting a value to a rese rved bit, access in byte units. table 18.3 pdr register settings in 64-pin packages port symbol pdr register b7 b6 b5 b4 b3 b2 b1 b0 port0 1 1 1 1 1 1 port1 1 1 1 1 p o r t 2 111111 p o r t 311011 port4 1 1 port5 1 1 1 1 1 1 porta 1 1 1 portb 1 1 portc porte p o r t j 111111
page 4 of 4 renesas technical update tn-rx*-a0 a/e d ate: ) h e . , 2014 table 18.4 pdr register settings in 48-pin packages table 18.5 pdr register settings in 40-pin packages table 18.6 pdr register settings in 36-pin packages port symbol pdr register b7 b6 b5 b4 b3 b2 b1 b0 p o r t 011111111 port1 1 1 1 1 p o r t 2 111111 p o r t 311011111 port4 1 1 1 1 p o r t 511111111 porta 1 1 1 1 portb 1 1 1 1 portc porte 1 1 p o r t j 111111 port symbol pdr register b7 b6 b5 b4 b3 b2 b1 b0 p o r t 011111111 port1 1 1 1 1 p o r t 2 111111 p o r t 311011 11 port4 1 1 1 1 1 p o r t 511111111 porta 1 1 1 1 portb 1 1 1 1 1 1 p o r t c111 1111 porte 1 1 1 p o r t j 111111 port symbol pdr register b7 b6 b5 b4 b3 b2 b1 b0 p o r t 011111111 port1 1 1 1 1 p o r t 2 1111111 p o r t 311011111 p o r t 411111 1 p o r t 511111111 porta 1 1 1 1 1 portb 1 1 1 1 1 1 p o r t c111 1111 porte 1 1 1 p o r t j 111111
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